• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
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    • 专利摘要:
    Disclosed is a method for avoiding pixel saturation in a group of pixels, each having a node, in which a reference voltage is predetermined, and in which a voltage change at the node of only one of the pixels. compared to the predetermined reference voltage causes synchronous reset of all pixels of the group.
    公开号:BE1022491B1
    申请号:E2014/0067
    申请日:2014-02-06
    公开日:2016-05-04
    发明作者:Olivier Bulteel；Der Tempel Ward Van
    申请人:Softkinetic Sensors Nv；
    IPC主号:
    专利说明:

    Method for avoiding pixel saturation
    Technical field of the invention
    The present invention relates to the field of CMOS pixels with extended dynamic range and associated sensors. In particular, the present invention relates to improvements in, or relating to, the robustness of pixels against incident light by detecting and avoiding pixel saturation. By robustness we understand the ability of pixels to perform their light quantization function.
    Background of the invention
    An image sensor is a device capturing and transforming incident electromagnetic radiation such as a light flux into an electronic signal. In digital imaging, we mainly use Active Pixel Sensors (APS). APSs are image sensors consisting of an integrated circuit containing a matrix of pixel sensors, and wherein each pixel contains a photodiode and an active amplifier. There are many types of Active Pixel Sensors, including complementary metal oxide semiconductor (CMOS) APS, most commonly used in mobile phone cameras or webcams, for example. Such image sensors have emerged as an alternative to Charge Coupled Circuit (CCD) image sensors.
    In an APS, the photodiode is sensitive to incident light. More specifically, the photodiode transforms the incident light into charges that are accumulated during a given exposure time and then transformed into an amplified voltage within the pixel. This voltage is a continuous analog physical quantity which can be converted, by means of an analog-digital converter, into a digital number representing the voltage amplitude. The cathode terminals of the photodiode, referred to as the node attached to the cathode, are often referred to as the detector node. This node (20) is shown in FIG. 1 representing a pixel of APS. The voltage at this node is translated to the pixel output via a transistor used as an amplifier. An important quality factor characterizing pixels is what is called their fill factor. It refers to the light-sensitive area portion, in percentage, relative to the entire pixel area. Figure 2 shows a conventional pixel surface divided into a photosensitive surface 1 and a circuit surface 2.
    One of the major drawbacks of standard pixels is their potential saturation occurring when too much incident light and / or too long exposure occur.
    In a range-based imaging system using Time-of-Flight (ToF) technologies, for example a Time-of-Flight camera system providing distance information by analyzing the Flight Time and the phase of a flight. a pulsed light signal emitted by a light source controlled and reflected by objects in the scene, saturation may occur when objects having standard reflective properties are closer to the range of distances for which the imaging system is calibrated . The object then reflects too much of the emitted light and causes at least some sensor pixels to respond to their maximum value. Saturation can also occur when objects demonstrate specular reflective properties in the wavelength range at which pixels have been designed to be sensitive, such as when a mirror in a scene reflects the entire incident light it receives on the sensor reflecting the scene, or when objects reflect and focus the incident light on a portion of the sensor, or when an external light source emitting intense illumination in the same wavelength range for which the recording apparatus ToF views was designed illuminates the sensor. When pixels are saturated, significant scene information is lost since the response provided is flattened to the maximum voltage value that can be supplied; this leads to image artifacts or defects, such as a burned surface, blurring effects in images. In addition, some applications, for example, computing depth information in a ToF technology, use a phase shift based on calculations from a plurality of captures to obtain a distance measurement. If pixel saturation occurs during the integration time, the voltage at the detector nodes reaches a saturation level that corrupts the corresponding capture. This makes it more particularly possible to determine relative voltage magnitudes between the different phases impossible and therefore the depth measurements and the corresponding depth map can not now be determined as is usually obtained directly from these difference calculations. phase.
    In order to overcome saturation problems, among other things, the Extended Dynamic Range (HDR) or Extended Dynamic Range (WDR) has been proposed in standard image sensors using several electronic circuits, for example the flip-flop. Schmitt (as defined in this document below) with the addition of latches and / or a memory point. Sensors have also been designed with techniques such as good fit, multiple captures, or variable exposure in space. In addition, additional logic circuits have been added by APS CMOS, but this reduces the effective sensor surface area and results in a very low fill factor that does not comply with effective ToF imaging requirements. Another solution is to use circuits with logarithmic pixels.
    Such pixel circuits produce a voltage level which is a logarithmic function of the amount of light striking a pixel. This differs from most CMOS or CCD type image sensors that use a linear type of pixel. Nevertheless, the use of logarithmic pixels greatly complicates the post-processing to compute the necessary data, such as depth information, since this introduces well-known compression problems and also requires additional processing calculations. SUMMARY OF THE INVENTION The object of the invention is to improve the robustness of pixels against the incident light by avoiding their saturation. To this end, the invention relates first of all to a method according to claim 1. The invention is furthermore particularly adapted to the context of time-of-flight imaging where an active infrared modulated light illumination is controlled at high frequencies and where the lighting signal to be measured may suffer from ambient light coexisting in the scene, or reflective powers and varying distances of objects in the scene.
    Therefore, an advantage is that because of the use of the synchronous reset pixel, saturation is avoided in the pixel group, which avoids image artifacts.
    An additional advantage is that by avoiding pixel saturation during the integration time, the present invention avoids the neighboring pixels of a pixel that would have saturation without being reset to be corrupted by load migration. and by the associated blur default artifact.
    In addition, by avoiding pixel saturation, the present invention also makes it possible to prevent the sensor from suffering from blurring effects and associated image artifacts.
    An additional advantage is that because of the sharing of the saturation circuits between several pixels, the fill factor is kept high, and the additional circuits are limited.
    A further advantage is that because of the use of the synchronous reset pixel, the information carried by the voltage amplitudes at the pixel detector nodes is not corrupted by saturation, which allows calculate relative amplitudes and / or phase differences between the nodes. -
    Accordingly, in the TOF imaging context, the measurement of data is preserved and allows the determination of distance information.
    Advantageously, the reset of all the pixels is allowed at least once in a given integration time Tint by a validation signal which may be a pulse, a clock, or a pulse wave with a tunable period and / or a duty cycle.
    Preferably, absolute measurements of Extended Dynamic Range can be evaluated. From the number of synchronous resets that may have been triggered during each integration time, or from the time at which the last synchronous reset was triggered combined with the detector node voltage unsaturated from the individual pixel nodes, the total absolute voltages corresponding to an incident light received during the entire integration time can be evaluated. The invention also relates to a synchronous reset pixel device according to claim 18 and to an imager according to claim 19. Other advantages and new features of the invention will become more apparent from of the detailed description which will follow when taken in conjunction with the accompanying drawings.
    Brief description of the drawings
    The present invention will be better understood in light of the following description and the accompanying drawings. FIG. 1 describes a standard 3-transistor Active Pixel Sensor composed of a photodiode 3, a reset transistor 4, a transistor used as an amplifier 5 and a transistor for selecting a transistor. pixel 6; FIG. 2 represents a conventional pixel surface, divided into a photosensitive surface 1 and circuit surfaces 2; FIG. 3 represents a conventional voltage drop, at the nodes of a group of 4 pixels, without incident light; FIG. 4 represents an example of voltage drop at the nodes of the same pixels introduced in FIG. 3, under a strong incident light; FIG. 5 compares the effects of a standard comparator (A) with those of a Schmitt trigger (B) on an input signal (U); FIG. 6 represents a block diagram of a synchronous reset pixel composed of 4 Active Three-transistor Transistor Sensors (7, 8, 9, 10), a lowest voltage detector block 11, a comparator 12 and an additional transistor 13 added to each APS at 3-T; FIG. 7 describes the synchronization scheme of the synchronous initial reset pixel with a comparator, as previously discussed in FIG. 6; FIG. 8 represents a block diagram of the same synchronous reset pixel as in FIG. 6, but with the addition of an ENCOMP pin 14 connected to the comparator; Fig. 9 shows the timing diagram referring to the synchronous reset pixel shown in Fig. 8, with an effective integration time of TW-Ten; FIG. 10 shows the timing diagram referring to the synchronous reset pixel shown in FIG. 8, with an integration time of; FIG. 11 represents a block diagram of the same synchronous reset pixel as in FIG. 6, but with the addition of an ENCOMP pin 14 connected to both the comparator and the lowest voltage detector ; Fig. 12 shows the timing scheme referring to the synchronous reset pixel shown in Fig. 11, with an effective integration time of TW-Ten; FIG. 13 represents the timing diagram of the synchronous reset pixel represented in FIG. 11, but with the substitution of the pulse of the ENCOMP pin 14 by a clock, in which 2 saturations occur; FIG. 14 represents the synchronization diagram of the synchronous reset pixel represented in FIG. 11, but with the substitution of the pulse of the ENCOMP pin 14 by a clock, with a tunable reference voltage and a tunable clock period; FIG. 15 represents the timing diagram of a synchronous reset pixel, in which a signal STOP_SRST is used in order to prohibit SRST; FIG. 16 represents the synchronization diagram of the synchronous reset pixel represented in FIG. 11, but with the substitution of the pulse of the ENCOMP pin 14 by a constant clock, and an ENSRST signal with a period tunable clock; - Figure 17 describes a standard Bayer matrix with 2 green pixels, a blue pixel and a red pixel; FIG. 18 describes the same matrix as in FIG. 17, but with a single green pixel replaced by a synchronous reset pixel acting as a saturation detector; FIG. 19 represents a matrix of depth pixels with a single synchronous reset pixel in groups of 9 pixels; and - Figure 20 shows a depth detection pixel matrix with a single synchronous reset pixel per group of 5 pixels; FIG. 21 represents a matrix of depth detection pixels with a single synchronous reset logic shared over a group of 4 pixels. The surface is divided into a photosensitive surface 15, the associated pixel circuit surface 16, and the synchronous partition reset logic 17.
    Description of the invention
    The present invention relates to a synchronous reset pixel that can be classified as an Extended Dynamic Range pixel system and the associated method. The pixel may comprise at least one photodiode, each photodiode having its own detector node. The present invention is capable of returning a group of local pixels to the initial state, which empties the detector nodes of the pixels of the accumulated charges during an exposure. The reset can be triggered when one of the voltages corresponding to these loads reaches a predetermined threshold voltage value. This prevents the detector nodes from reaching a saturation level before or at the end of the integration time. The principle relies on comparator-based logic circuits that detect at least once the attainment of the predetermined threshold voltage for a given integration time. The logic is shared by a group of pixels to minimize the silicon area involved in the comparison task and to maintain the high fill factor so as to preserve the efficiency of the detection task. The logic allows a plurality of resets during the given integration time as the comparison task can be performed multiple times with respect to a predetermined series of occurrences (eg, Tint / 2, 3Tint / 4, 7Tint / 8, ...). When at least one of the pixels reaches the "saturation indication voltage", which is given by the previously mentioned predetermined threshold voltage, the logic may decide to reset the pixel group at the same time or not. In the context of TOF imaging in which a plurality of unsaturated amplitude measurements must necessarily be collected to calculate reliable phase differences and depth evaluations, the system and method of the present invention may be particularly well suitable for providing reliable information such as incident signal phases and relative values of incident signal.
    In the latter case, the absolute value of the incident signal may further be evaluated as the invention may include additional "reset counting circuits" and a method for determining the total amplitude of the signal collected during the integration time using this reset counter.
    For the sake of clarity, the present description will be described with regard to the depth calculation in 3D image sensors in Time of Flight (ToF) measurements, but the invention is not limited thereto, as we will see it below afterwards. The invention could be useful for any type of sensor where pixel saturation is to be avoided.
    The embodiments introduced will be described according to the use of a Schmitt trigger as comparator means 12, but the invention is not limited thereto. The comparator 12 may for example be made by a continuous time comparator or a clocked comparator, a CMOS inverter or any sort of circuit capable of producing a pulsed signal from the output of the lowest voltage detector block 11 like a monostable circuit.
    In addition, to address the synchronous reset function, a lowest voltage detector block can be used to seek the lowest voltage as in a three-PSA APS (3T), Figure 1 In this case, the detector voltages drop from Vreset to ground as shown in Fig. 3 and Fig. 4. Of course, a higher voltage detector block could be mentioned in the case where the detector voltages would have been detected. increased from Vreset to the diet.
    Time-of-flight camera systems are known to provide distance information to an object by analyzing the flight time from a light source to the object and back. In these systems, a scene is illuminated with a modulated light, usually a pulse. This signal is then reflected by objects and collected by a lens to form an image. Depending on the distance of objects from the camera, there is a delay between the emission of the modulated light and the reception of its reflection at the camera. This delay, or phase, which can be obtained over time and / or during successive pulses, is used to determine a direct measurement of the distance of an object in the scene. It is therefore mandatory to have reliable unsaturated signal measurement data from the sensor.
    Fig. 3 shows an example of sensor node (cathode photodiode) waveforms versus time in a TOF imager without incident light. Before the start of the TinT integration or exposure time, the RESET signal is held high to reset all detector nodes to the initial and appropriate voltage states. When the RESET signal is released, the integration time starts. At the end of the integration or exposure time T [nT, none of the detectors is saturated and the depth information can be calculated. Conversely, Figure 4 shows the same installation as in Figure 3, but subjected to strong incident light. The voltage at the detector nodes DET2, DETi and DET / drops too rapidly before the end of the integration time TdmT. These 3 detector nodes are saturated, the absolute values collected at the end of the integration time of the corresponding pixels are corrupt and meaningless. By corrupted, this means that the determined voltage values are unreliable since they do not represent a real absolute measurement representative of the input light signal. As a result, the relative magnitudes of pixels are also corrupted and the associated phase information also, rendering the depth information now impossible to calculate.
    FIG. 1 represents a standard CMOS sensor with 3 active transistors (CMOS 3-T APS), consisting of a photodiode 3, a RESET transistor 4, a source-loaded reading transistor 5 and a transistor SELECTION 6. When the transistor RESET 4 is turned on, photodiode 3 is directly connected to the VDD power supply and all integrated loads are erased. The charged source read transistor 5 acts as an amplifier which allows the pixel voltage to be observed without removing the accumulated charge. The SELECTION transistor 6 allows a single row of the pixel array to be read by the readout electronics. In order to achieve a high fill factor, the light-sensitive surface of photodiode 3 should be high, while the surface of the circuits, consisting of the surface of transistors 4, 5 and 6, should be as small as possible.
    For the sake of understanding, a particular electronic circuit used in additional embodiments of this invention must be introduced: the Schmitt flip-flop. In the non-inverting configuration, a Schmitt trigger is a circuit with a positive feedback and a loop gain greater than 1. It can be likened to a comparator circuit with a hysteresis. Figure 5 compares the effects of a standard comparator (A) and a Schmitt trigger (B) on a given input signal (U). By using a non-inverting Schmitt flip-flop, when the input is above a certain threshold, the output is high. When the input is below a different (lower) set point, the output is low, and when the input is between the two levels, the output retains its value. This double threshold action is called hysteresis and implies that the Schmitt trigger has memory and can act as a bistable circuit.
    By comparison, a standard comparator has only one threshold value and its output is switched by comparison to that value, as shown in Fig. 5 (A).
    Fig. 6 shows a first embodiment of the present invention with a synchronous reset pixel dealing with 4 pixels each having at least one detector node. It is made of 4 CMOS APS 3-T 7, 8, 9, 10, a lowest voltage detector block 11 having 4 inputs, a comparator 12 and an additional transistor 13 added to each APS 3-T (thus in total 4 additional transistors). The photodiodes of APS 3-T need not be identical. The lowest voltage detector inputs 11 detect the detector nodes of the 4 APS: DET0, DET], DET2 and DET3. Here, the comparator 12 can be made either by a comparator comparing DETX with a reference voltage VREf or by a Schmitt flip-flop having its lower detection threshold equal to VREF, or any sort of circuit capable of producing a pulsed signal from the output of the lowest voltage detector block, such as a monostable circuit. The functionality of resetting transistors 13 can be obtained by dedicated logic circuits and by the reuse of the RESET transistors of the APS 3T.
    FIG. 7 describes the synchronization scheme of the synchronous reset pixel presented in FIG. 6. Thanks to the lowest added voltage detector 11 added and the comparator 12, the pixels are not saturated after a period of time. Tait integration. Indeed, as soon as one of the pixel voltages reaches the voltage VREf, the signal SRST goes high and returns all the pixels to the initial state. So pixel saturation is avoided.
    FIG. 8 represents a second embodiment of the present invention, a block diagram of the synchronous reset pixel but with the addition of an ENCOMP pin 14 connected to the comparator 12. This ENCOMP pin 14 is added to define a shorter integration time (Tint-TEn). Indeed, detectors that crossed the reference signal before the ENCOMP pulse will resume their integration cycle, but with a shorter time so that the saturation until the end of the exposure time Tint is impossible for these pixels. TEN is programmable and must be set to avoid pixel saturation. A high level of the ENCOMP signal may be rather short and should be long enough to completely reset the pixels.
    FIG. 9 shows the timing diagram of the synchronous reset pixel as shown in FIG. 8, including the lowest voltage detector 11 and the comparator 12 plus its ENCOMP pin 14. The comparator 12 can only switch its output if the ENCOMP signal is set high. When the ENCOMP signal is low, the pixels may saturate as if there were no additional circuits.
    On top of that, an SRST_CNT signal is added and is high as soon as there is a pulse on the SRST signal. Thanks to the signals ENCOMP and SRST_CNT, the integration time can easily be calculated. At the end of the exposure, the integration time is either (Tint -Ten) if the FLACE signal is high or Tint if the FLAG signal is low. Figure 9 and Figure 10 represent the two cases.
    The signal SRST_CNT can be considered as a 1-bit counter.
    Instead of a basic 1-bit counter, the saturation detector circuits could incorporate an n-bit counter and output the information as an output.
    By using such a counter, the absolute value per detector (pixels) is known in addition to the relative values of each.
    In this embodiment, using a comparator or inverter instead of a Schmitt flip-flop, the high level duration of the ENCOMP pin can be chosen in such a way that the reset level can be identical to the initial level. Schmitt latch limitations, such as the inability to reach VREset during a synchronous reset, are overcome.
    A third embodiment is shown in FIG. 11. FIG. 11 shows a block diagram of the synchronous reset pixel but with the addition of an ENCOMP pin 14 connected to both the lowest voltage detector 11 than comparator 12.
    FIG. 12 shows the same input conditions as FIG. 9. The only change is in the ENCOMP pin 14, connected to both the lowest voltage detector 11 and the comparator 12. DETX copies the lowest voltage between DET0 , DET ^ DET2 and DET3 only when the ENCOMP signal is high. The result for the SRST and SRST_CNT signals is identical for both configurations.
    These second and third embodiments have the advantage of saving power as the lowest voltage detection and comparison is only performed when the ENCOMP signal is set high. Indeed, the comparator 12 functions as an analog "voltage comparator" and its current consumption will be related to its input voltage. With the addition of the ENCOMP pin 14, the comparator 12 and from time to time the lowest voltage detector 11 will only consume current a fraction of the time compared to the case without ENCOMP pin 14, as the ENCOMP signal is disabled the most of the time.
    A fourth embodiment is shown in FIG. 13, where the ENCOMP signal is replaced by a clock signal instead of a single pulse. The clock can be considered as a pulse train and therefore the comparison process occurs more often. This embodiment is useful for applications requiring only relative voltage differences between pixel detector nodes and no voltage amplitude. Such an application could be the depth calculation for example, as previously described in this document. In FIG. 13, two saturations occur and the signal SRST_CNT has been raised as soon as the first pulse SRST appears.
    In this example, a 1-bit counter is not sufficient as there were 2 SRST pulses. However, the integration of a 2-bit counter would be sufficient to find the correct number of SRST events. The relative voltages between the DET nodes are correct but the absolute magnitudes are not correct without the aid of the 2-bit counter. In the context of ToF, the relative data measures are quite appropriate for pixel depth value estimates.
    A fifth embodiment is described in FIG. 14 which describes an example of optimized synchronization schemes obtained with the proposed synchronous reset pixel of FIG. 13. It will be noted that 2 parameters (ENCOMP signal period and voltage reference VREF) are changed during the integration time. The ENCOMP period varies from T to T / 16, where T is the reference period which could be equal to half of TLNT, and the reference voltage VREF varies from Vreseto A VRESETO2 to a scale of 2. The purpose of these variations is optimize the signal amplitudes at the end of the integration time. These variations are optimized and based on the fact that the voltage drops at the pixel nodes are linear. The minimum ENCOMP period produced and the reference voltage could be less than T / 16 and would ideally even tend to 0. This statement is also valid for the reference voltage VREF. The ENCOMP period and the reference voltage values are chosen to be simple and are given as an indication for the sake of clarity but obviously we can find some other configurations (adding a constant offset, adding a gain to each of the values ) that will lead to the same functionality.
    A sixth embodiment is described in FIG. 15. In this embodiment, the reference voltage does not vary anymore and is kept constant at Vreset / 2 · The ENCOMP signal period always varies. The SRST signal still allows the reset of all detector nodes when it is high. However, there is now the addition of a STOP_SRST signal that prohibits the SRST signal only when the STOP_SRST signal is high. When the ENCOMP signal is high, the signal STOP_SRST can either be set low if the DETX node is lower than the reference voltage VREF or set high if the DETx node is greater than the reference voltage VREF. For example, in Figure 15, at the beginning, STOP_SRST is set low by the RESET signal. Then, at time T1, the first pulse of the ENCOMP signal occurs, DETX is less than VREF, so STOP_SRST is kept low, SRST is allowed to trigger the reset. At time T2, the same conditions as at time T1 are satisfied, so the signal SRST establishes a pulse. However, at time T3, DETX is greater than VREF, therefore the signal STOP_SRST is set high which prohibits the SRST pulse.
    Once the signal STOP_SRST is set high, it remains at this level until the end of the integration time the TW. The detectors will not reach saturation assuming the incident light is constant throughout the integration time Tint. Other clock period and voltage reference configurations may lead to results similar to those previously described. In practice, it may be necessary to use margins to determine the reference voltage. For example, initial VREF can become Vreset / 2 +/- VoFFSET ·
    A seventh embodiment is introduced in FIG. 16. It has the advantage of preventing any of the nodes from reaching saturation in comparison with FIG. 15. By doing so, any kind of effect blur is avoided. The blur can be induced when at least one of the detector nodes saturates, meaning that its associated pixel well capacity is reached and any additional photons could migrate charges into the neighboring pixel well. In this embodiment, a reference voltage is used which does not vary and is kept constant at Vresetc · The ENCOMP signal is now used as a clock with a constant period. There is another signal called ENSRST which is a signal with a changing period ofTaT / 16 at a scale of 2, where T is the reference period which could be equal to half of Tint-
    When the ENCOMP signal is high and the STOPJSRST signal is low, the lowest voltage detector is enabled and DETX reproduces the lowest voltage between the detector nodes. When the signal ENCOMP is high and the signal STOP_SRST is low, if the signal DETX is lower than the reference voltage VrEF, then the signal SRST is set high, which allows the restoration to the state initials of all detector nodes. On the other hand, when the signal ENCOMP is high and the signal STOP_SRST is low, if the signal DETX is higher than the reference voltage VREF, then the signal SRST is set low. Once the signal SRST is set high, it will remain at this level until a pulse on the signal ENSRST is received. If STOP_SRST is high, the lowest voltage detector is not enabled, so DETx does not reproduce the lowest voltage between detector nodes. STOP_SRST is set low at the beginning of the integration time. It is set high whenever SRST is low when a pulse on ENSRST occurs. Once it is set high, it stays at this level until the end of the integration time. This means that the detector nodes will not be saturated at the end of the integration time.
    For example, in FIG. 16, at the instant T1, SRST is set high as DETX is smaller than the reference signal VREE.
    As a result, the DET nodes are reset, which prevents any detector node from saturating and potentially filling its pixel well, thus avoiding blur. SRST will remain high until an ENSRST pulse is received which occurs at time T2. At time T2, another integration phase occurs and as SRST is high, STOP_SRST remains low. Then, another saturation is detected at time T3 and SRST is again set high. SRST will be released by an ENSRST pulse at time T4 and an integration phase starts again and STOP_SRST always remains low. At time T5, ENSRST should not release SRST as no saturation was detected between times T4 and T5. So, STOP_SRST is set high as SRST is low. As a result, the integration will continue until the end of the integration time Tint. Other clock period and voltage reference configurations may lead to results similar to those previously described in this document. In practice, margins may have to be taken for the reference voltage. For example, initial VREf can become Vreset / 2 + Voffset ·
    In a further preferred embodiment, the system and method previously described herein may be implemented in an HDR context. Indeed, in HDR, it is necessary to measure or evaluate the real absolute value of the incident light at the node.
    The method and the device previously described in this document make it possible to obtain a valid, significant, reliable voltage amplitude corresponding to the light measured at the end of the integration time. By associating a counter with the logic to keep track of the number of resets performed during this integration time, it may be possible to measure or obtain the absolute voltage magnitude appropriate for implementation. HDR.
    Considering the linearity of the voltage drop at the node and considering the incident light power as a constant over time, the absolute measurement of extended dynamic range can correspond to: - the sum of the amplitude measurement of the final voltage at the node to which is added the voltage magnitude value corresponding to the difference between the reference voltage and the synchronous reset voltage times the number of synchronous resets or. an extrapolation of the final voltage amplitude measurement obtained for the last integration time (= well-known fraction of the integration time), knowing the number of synchronous resets counted.
    For the sake of clarity, the present description has been previously described with respect to the depth calculation in a 3D image sensor in a Time of Flight (TOF) measurement, but the invention is not limited to that. .
    Among the TOF imagers, the synchronous reset pixel, presented above, could be applied to conventional imagers. For example, Figure 17 and Figure 18 show how the proposed innovation could be applied to a matrix of color pixels such as the standard Bayer matrix (Figure 17) or the Foveon-based color detection architecture, or any other detection system with light capture. For example, in a color sensor based on a standard Bayer matrix, the second usual green pixel could be replaced by a synchronous reset pixel responsible for detecting the saturation of the remaining color pixel: blue, green and red, as shown in Figure 18. In order to give more intensity to the green pixel and to compensate for the loss of the second green pixel, some imager process techniques could be applied as light pipes, quantum dot films or microlenses for example.
    In "depth" imagers, the proposed synchronous reset pixel system and method could be used as shown in Figure 19 and Figure 20, describing two possible pixel organizations. They could further be extended to an "in-pixel" embodiment of architecture in which each pixel could comprise a plurality of detector nodes and synchronous reset circuits for comparing voltages at these levels. nodes to reset at least the nodes of each individual pixel if saturation is detected at these detector nodes. Optionally, the neighboring pixels of the aforementioned embodiment could also be reset to preserve the system with a risk of blur. The proposed synchronous reset pixel is careful either to control adjacent incident lights or to control its own incident light for the entire group. For the first case, if one of these adjacent pixels saturates, then the entire group is reset at the same time. For the second case, if the central pixel saturates, then the entire group is reset at the same time. In Figure 19, a single synchronous reset pixel (SAT DET) is placed in groups of 9 pixels while in Figure 20 a single synchronous reset pixel (SAT DET) is placed in groups of 5 pixels.
    In addition, the synchronous reset logic does not have to be embedded in a dummy pixel. It could be part of the circuit surface 2 of FIG. 2. In fact, the synchronous reset logic can also be integrated inside the circuit surface as described in FIG. Figure 21 shows a specific configuration, but obviously there are many more possible configurations.
    Translation of drawings:
    f ". *
    权利要求:
    Claims (20)
    [1]
    claims
    A method for preventing pixel saturation in a group of pixels during an integration time Tint, each having a detector (3) and a detector node (20), the method comprising the steps of: - predetermining a voltage of reference for which the saturation of the pixels is not reached, - comparing the voltage at the detector node of each pixel with the predetermined reference voltage during the integration time; and - causing the detectors of all the pixels in the group to reset to synchronous state when a voltage at the detector node of only one of the pixels reaches the predetermined reference voltage.
    [2]
    2. Method according to claim 1, wherein the reset of the detectors of all the pixels is allowed during the integration time Tint, by at least one authorization signal.
    [3]
    The method of claim 2, wherein the authorization signal is a validation signal (ENCOMP) for allowing the detectors to reset all the pixels just once.
    [4]
    The method of claim 2, wherein the authorization signal is a pixel clock signal to allow the detectors to reset all the pixels at least once.
    [5]
    The method of claim 4, wherein the pixel clock signal has a period that varies during the TINT integration time.
    [6]
    The method of claim 5, wherein the variable period of said pixel clock signal is consecutively decreased by a predetermined factor a to form a series of occurrences at which the reset of the detectors of all the pixels are validated when the voltage at the detector nodes reaches the predetermined reference voltage.
    [7]
    The method of claim 6, wherein the predetermined factor a is 2, as the variable period of the pixel clock signal becomes sequentially Tint / 2, Tint / 4, Tint / 8, Tint / 16 and T | NT / 32 to a predetermined discrete finite number.
    [8]
    The method of any one of claims 1 to 7, wherein the threshold voltage is a variable voltage.
    [9]
    The method of claim 8, wherein the threshold voltage level is decreased consecutively by a predetermined factor β.
    [10]
    The method of claim 8, wherein the predetermined factor β is 2 as the threshold variable voltage level becomes sequentially Vreset> Vresf.to, Vreset / 4) Vreset / 8 »Vreset / 16 and Vreset / 32 until 'to a discrete finite number.
    [11]
    The method according to claim 1 to 7, wherein the synchronous reset is prohibited by a STOP reset signal (STOP SRST) until the end of the integration time when the saturation is not reached.
    [12]
    The method of claim 3 to 11, wherein the ENCOMP signal continues to reset the pixel detectors until a reset enable pulse (ENSRST) is received.
    [13]
    The method of any one of claims 1 to 11, wherein a reset counter signal (SRSTCNT) is set high if at least one saturation occurs.
    [14]
    The method of claim 12, wherein the signal SRST CNT is an n-bit COUNTER which counts the number of saturations occurring.
    [15]
    The method of any one of claims 1 to 13, wherein said group of pixels includes at least two pixels.
    [16]
    The method of claim 13 or 14, absolute Extended Range Measurements are evaluated based on i) the voltage at the pixel detector nodes at the end of the integration time and ii) the number of saturations. occurring counted.
    [17]
    The method of claim 1 to 16, wherein absolute Extended Range Measurements are evaluated based on i) the voltage at the pixel detector nodes at the end of the integration time and ii) the occurrence in the time at which the last reset occurred during the integration time.
    [18]
    A synchronous reset pixel device for implementation according to any one of claims 1 to 17, comprising: - a group of pixels, each of which comprises a detector (3) which is light-sensitive device, connected to a detector node (20), a RESET transistor (4), a source-source read transistor (5) and a SELECT transistor (6), - at least one voltage detector (11) ), which detects the voltage change at each of the pixel sensor nodes (20) and outputs a saturated pixel, - a comparative means, provided with a predetermined threshold voltage for which the saturation of the pixels is not attained, for comparing said predetermined threshold voltage with the voltage at the detector node (20) of said pixels, - means for allowing the pixel detectors to be reset for a given integration time TINT, - a way to count the number of satu rations occurring during said integration time Tint.
    [19]
    An imager comprising: - the synchronous reset pixel device according to claim 18, and - a pixel array connected to said device.
    [20]
    The imager of claim 19, further comprising means for flight time measurements.
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    EP131930687|2013-11-15|
    EP13193068.7A|EP2874388B1|2013-11-15|2013-11-15|Method for avoiding pixel saturation|
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